1. Field of the Invention
The disclosure relates generally to refreshing non-volatile memory devices, more particularly, relates to a method of partially refreshing non-volatile memory devices to decrease the time needed for erasing thereof.
2. Description of the Related Art
A flash memory device is a specific type of non-volatile memory by which bits of logical data are stored in memory cells. A grouping of memory cells is a word, a grouping of words is a page, and a grouping of pages is a sector. Data is accessed for reading and programming by words or pages, and an entire sector must be accessed for erasing. In general, the flash memory is arranged into columns and rows of memory cells, wherein each column represents a bit line of a data.
Voltages can be applied to the transistor for setting the VT (programmable threshold voltage), to represent a logical value “1” or “0,” for reading the data stored in the memory cell, for verifying that the cell has been programmed, for verifying that the cell has been erased, and for verifying that the cell has not been over-erased. When a voltage sufficiently exceeding the VT is applied to the control gate, the transistor turns on and can conduct a substantial current. Conversely, when a voltage applied to the gate does not sufficiently exceed the VT, the transistor will remain in an off state and will not conduct a substantial current. In typical flash memory designs, the on state represents a logical “1” while the off state represents a logical “0.” For example, during a read cycle of a programmed memory cell, the voltage applied to the gate is not greater than VT, and the memory cell will not conduct current. In comparison, an erased memory cell will conduct current during a read cycle because the gate voltage is greater than VT. Thus, a programmed memory cell represents logical “0,” while and erased memory cell represents logical “1.”
It is well known that flash memory devices have a limited number of erase-program cycles before they can no longer be used to store data reliably. More specifically, flash memory cells are subject to program/erase cycle wearing, which is a progressive degradation of a flash memory cell due to cumulative program and erase operations. Those skilled in the art will understand that a memory block is always erased first prior to being programmed with data, hence the cycles can be referred to as both program and erase cycles. Those skilled in the art will also understand that partial erase within a physical block is practicable as long as unselected portion of the physical block is properly counter-biased. However, the unselected portion may still need to be refreshed to guarantee the cell integrity. When memory cells are degraded, higher program and erase voltages are needed to program or erase the memory cells to the desired threshold voltages. Eventually, the memory cells will fail to retain data properly, which is represented as a programmed threshold voltage.
This problem is compounded by the fact that the block size of flash memory devices continues to increase while the data file sizes stored therein remain relatively static. For example, block sizes for present day high density flash devices are in the range of 256 KB, but future high density flash devices will have block sizes approaching 512 KB. If the data file stored in the block is small, then more memory cells will be unnecessarily subjected to erase/program cycles relative to a block have the size of the data file when the data file is modified.
Accordingly, an effective erase method is desired, which reduces unnecessary erase time and reduces the erase time of each cycle for extending the life span of the flash memory.